Author MoneyDJ | Release Date July 15, 2024 11:35 | Category Semiconductor, Packaging Test

The emergence of new applications such as AI has led to a continued hot topic in advanced packaging, with FOPLP (Fan-Out Panel Level Packaging) technology once again taking center stage. According to industry reports, leading semiconductor foundry TSMC has officially formed a team and is planning to establish a mini line during the "Pathfinding" phase with a clear goal in mind.

TSMC developed the InFO (Integrated Fan-Out) packaging technology in 2016, using the FOWLP (Fan-Out Wafer Level Packaging) technology for the A10 processor in the iPhone 7. Subsequently, semiconductor packaging and testing firms have actively promoted the FOPLP solution in order to attract customers with lower production costs, but the technology has yet to completely break through. Current end applications remain in mature processes, such as PMIC (Power Management IC) products.

However, industry reports suggest that TSMC's desire to transition advanced packaging technology from wafer level to panel level is no longer just talk on paper, but a serious move. The main plan is to use rectangular substrates, with dimensions of 515mm by 510mm, and the existing formal team is planning to establish a mini line.

A simple analysis suggests that TSMC's FOPLP can be seen as a rectangular InFO, with the added advantages of low unit cost and large-size packaging, integrating TSMC's 3D fabric platform and other technologies to develop advanced packaging such as 2.5D/3D for high-end product applications. It can be seen as a rectangular CoWoS, targeting AI GPU products, with Nvidia as a customer. If progress goes smoothly, the products may debut in 2026-2027.

AMD's early partners for FOPLP are United Microelectronics Corporation (UMC) and Siliconware Precision Industries Co., Ltd. (SPIL), with end applications possibly being used in PC or gaming chipsets. Industry analysts suggest that in the past, PC and gaming console packaging methods were mainly based on FC-BGA, with new products possibly upgrading to CoWoS level. Due to the high cost sensitivity of such consumer products, IC design companies are actively seeking more cost-effective advanced packaging solutions, with the earliest products possibly being launched in 2027.

Semiconductor industry insiders believe that in the early stages of FOPLP development, only SPIL, ChipMOS Technologies, and UMC were involved, with progress being inconsistent. In order to allocate resources correctly, equipment manufacturers have had a more conservative investment approach, mainly making major specification changes to please customers. With TSMC's formal involvement, the equipment manufacturers have now turned more proactive in preparing for battle.

In summary, the development of the FOPLP ecosystem still depends on TSMC, who continues to control the highest-end positioning, while packaging and testing firms target the mid to high-end markets. In the high-speed computing field, CoWoS is expected to remain dominant in the next three to five years, with the leading SoIC 3D packaging also making a big impact in the high-end market, which is also TSMC's main battleground.

For packaging and testing firms, the most important tool will be product upgrades combined with cost-effectiveness. The success of FOPLP as a new generation of advanced packaging solution will depend on the chip makers' product positioning, yield issues, and overall performance-to-price ratio, in order to make customers feel that they are getting value for their money.

(Original text: This article is authorized and reprinted by MoneyDJ News; Source of the first image: TSMC)